1. Field
The exemplary embodiments described herein are related to substrate processing systems and particularly to substrate transport systems, transport carriers, transport to processing tool interfaces and arrangements.
2. Brief Description of Related Developments
The prime forces on the fabrication of electronic devices are the consumer desire for more capable, and smaller electronic devices at lower costs. The primal forces translate to an impetus on manufacturers for further miniaturization and improvements in fabrication efficiency. Manufacturers, thus seek gains wherever possible. In the case of semiconductor devices, the conventional fabrication facility or FAB has at its heart (or base organizational structure) the discrete processing tool, for example a cluster tool, for performing one or more processes to semiconductor substrates. Conventional FABs are hence organized around the processing tool, that may be arranged in desired configurations to transform the semiconductor substrates into desired electronic devices. For example, the processing tool may be arrayed in the conventional FAB in processing bays. As may be realized, between tools, substrates may be held in carriers, such as SMF's, FOUP's, so that between tools substrates in process may remain in substantially similar cleanliness conditions as within the tools. Communication between tools may be provided by handling systems (such as automated material handling systems, AMHS) capable of transporting substrate carriers to the desired processing tools in the FAB. Interface between the handling system and processing tool may be considered for example purposes as having generally two parts, interface between handling system and tool to load/unload carriers to the loading stations of the processing tool, and interface of the carriers (i.e. (individually or in groups) to the tool to allow loading and unloading or substrates between carrier and tool. There are numerous conventional interface systems known that interface the processing tools to carriers and to material handling systems. Many of the conventional interface systems suffer from complexity resulting in one or more of the process tool interface, the carrier interface or the material handling system interface having undesired features that increase costs, or otherwise introduce inefficiencies in the loading and unloading of substrates in processing tools. The exemplary embodiments described in greater detail below overcome the problems of conventional systems.
Industry trends indicate that future IC devices may have about a 45 nm architecture or smaller. In order to increase efficiency and lower fabrication costs, it is desired that IC devices of this scale be manufactured using semiconductor substrates or wafers as large as possible. Conventional FABs are generally capable of handling 200 mm or 300 mm wafers. Industry trends indicate that in the future, it may be desirable that FABs handle wafers that may be larger than 300 mm wafers, such as 450 mm wafers. As may be realized, the use of larger wafers may result in longer processing times per wafer. Accordingly, with the employment of larger wafers, such as wafers of 300 mm or greater it may be desired to use smaller lot sizes for wafer processing in order to reduce work in process (WIP) in the FAB. Also smaller wafer lot sizes may be desired for specialty lot processing of wafers of any size, or for processing of any other substrates or flat panels including for example flat panels for flat screen displays. Though reduced WIP and efficient specialty lot processing is enabled by their use, nevertheless employment of small processing lots in the FAB may have a deleterious effect on conventional FAB throughput. For example smaller lot size, as compared to larger lot sizes, tend to increase the transport system burden for a transport system (transporting wafer lots) of a given capacity. This is illustrated in the graph shown in FIG. 51A. The graph in FIG. 51A illustrates the relationship between lot size and transport rate (expressed as moves per hour) for a number of different fab rates (expressed as wafer starts per desired periods such as per month, e.g. WSPM). The graph in FIG. 51A also shows a line indicating the maximum capacity of a conventional FAB handling system (e.g. about 6000-7000 moves per hour). Thus, the intersection between the handing system capacity line and the FAB rate curves identify the surfaces to lot size available. For example, to achieve a FAB rate of about 24,000 WSPM, with the given conventional transport system, the smallest lot size is about 15 wafers. The use of smaller wafer lots causes a reduction in FAB rate. Hence, it is desired to provide a system in which the wafer carrier, the interface between the carrier and processing tool, the carrier transport system (transporting carriers between tools, storage locations, etc. within the FAB) be arranged to allow use of wafer lots as small as one and as large as desired, without adversely impacting FAB rate.